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Commit 48993e49 authored by Mitalee Parikh's avatar Mitalee Parikh
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input design files2

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      docs/Input Devices.md
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      View file @ 48993e49
      ......@@ -56,9 +56,9 @@ Installed the symbol and footprint on KiCAD using [this guide](https://www.snape
      ![error](./images/input/error.jpg)
      ####Design Files
      ![Schematic](./images/input/t412+VEML6040-schematic.pdf)
      ![Schematic](./images/input/t412+VEML6040-schematic.pdf.zip)
      ![traces](./images/input/inverted-traces.png)
      ![outline](./images/input/t412+VEML6040rgbsensor-outline.png)
      [Schematic](./images/input/t412+VEML6040rgbsensor.sch)
      [traces](./images/input/traces.rml)
      [Kicad pcbnew](./images/input/t412+VEML6040rgbsensor.kicad_pcb)
      [Schematic](./images/input/t412+VEML6040rgbsensor.sch.zip)
      [traces](./images/input/traces.rml.zip)
      [Kicad pcbnew](./images/input/t412+VEML6040rgbsensor.kicad_pcb.zip)
      docs/images/input/t412+VEML6040-schematic.pdf deleted 100644 → 0
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      docs/images/input/t412+VEML6040rgbsensor.kicad_pcb deleted 100644 → 0
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      View file @ 95d84f32
      (kicad_pcb (version 20171130) (host pcbnew "(5.1.5-0-10_14)")
      (general
      (thickness 1.6)
      (drawings 6)
      (tracks 56)
      (zones 0)
      (modules 5)
      (nets 16)
      )
      (page A4)
      (layers
      (0 F.Cu signal)
      (31 B.Cu signal)
      (32 B.Adhes user)
      (33 F.Adhes user)
      (34 B.Paste user)
      (35 F.Paste user)
      (36 B.SilkS user)
      (37 F.SilkS user)
      (38 B.Mask user)
      (39 F.Mask user)
      (40 Dwgs.User user)
      (41 Cmts.User user)
      (42 Eco1.User user)
      (43 Eco2.User user)
      (44 Edge.Cuts user)
      (45 Margin user)
      (46 B.CrtYd user)
      (47 F.CrtYd user)
      (48 B.Fab user)
      (49 F.Fab user)
      )
      (setup
      (last_trace_width 0.4)
      (trace_clearance 0.4)
      (zone_clearance 0.508)
      (zone_45_only no)
      (trace_min 0.4)
      (via_size 0.8)
      (via_drill 0.4)
      (via_min_size 0.4)
      (via_min_drill 0.4)
      (uvia_size 0.3)
      (uvia_drill 0.1)
      (uvias_allowed no)
      (uvia_min_size 0.2)
      (uvia_min_drill 0.1)
      (edge_width 0.05)
      (segment_width 0.2)
      (pcb_text_width 0.3)
      (pcb_text_size 1.5 1.5)
      (mod_edge_width 0.12)
      (mod_text_size 1 1)
      (mod_text_width 0.15)
      (pad_size 1.524 1.524)
      (pad_drill 0.762)
      (pad_to_mask_clearance 0.051)
      (solder_mask_min_width 0.25)
      (aux_axis_origin 0 0)
      (visible_elements FFFFFF7F)
      (pcbplotparams
      (layerselection 0x010fc_ffffffff)
      (usegerberextensions false)
      (usegerberattributes false)
      (usegerberadvancedattributes false)
      (creategerberjobfile false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
      )
      (net 0 "")
      (net 1 SDA)
      (net 2 "Net-(0ohm1-Pad2)")
      (net 3 UPDI)
      (net 4 VCC)
      (net 5 "Net-(J1-Pad3)")
      (net 6 "Net-(J1-Pad4)")
      (net 7 "Net-(J1-Pad5)")
      (net 8 GND)
      (net 9 "Net-(M1-Pad2)")
      (net 10 TX)
      (net 11 RX)
      (net 12 "Net-(M1-Pad6)")
      (net 13 CLK)
      (net 14 /SCL)
      (net 15 "Net-(U1-Pad7)")
      (net_class Default "This is the default net class."
      (clearance 0.4)
      (trace_width 0.4)
      (via_dia 0.8)
      (via_drill 0.4)
      (uvia_dia 0.3)
      (uvia_drill 0.1)
      (diff_pair_width 0.4)
      (diff_pair_gap 0.25)
      (add_net /SCL)
      (add_net CLK)
      (add_net GND)
      (add_net "Net-(0ohm1-Pad2)")
      (add_net "Net-(J1-Pad3)")
      (add_net "Net-(J1-Pad4)")
      (add_net "Net-(J1-Pad5)")
      (add_net "Net-(M1-Pad2)")
      (add_net "Net-(M1-Pad6)")
      (add_net "Net-(U1-Pad7)")
      (add_net RX)
      (add_net SDA)
      (add_net TX)
      (add_net UPDI)
      (add_net VCC)
      )
      (module fab:fab-R1206 (layer F.Cu) (tedit 200000) (tstamp 60867A6B)
      (at 147.34486 123.325)
      (descr RESISTOR)
      (tags RESISTOR)
      (path /6077514B)
      (attr smd)
      (fp_text reference 0ohm1 (at 1.905 -1.905) (layer F.SilkS)
      (effects (font (size 1.27 1.27) (thickness 0.1016)))
      )
      (fp_text value RES-US1206 (at 2.54 1.905) (layer F.SilkS)
      (effects (font (size 1.27 1.27) (thickness 0.1016)))
      )
      (fp_line (start -1.6891 0.8763) (end -0.9525 0.8763) (layer F.SilkS) (width 0.06604))
      (fp_line (start -0.9525 0.8763) (end -0.9525 -0.8763) (layer F.SilkS) (width 0.06604))
      (fp_line (start -1.6891 -0.8763) (end -0.9525 -0.8763) (layer F.SilkS) (width 0.06604))
      (fp_line (start -1.6891 0.8763) (end -1.6891 -0.8763) (layer F.SilkS) (width 0.06604))
      (fp_line (start 0.9525 0.8763) (end 1.6891 0.8763) (layer F.SilkS) (width 0.06604))
      (fp_line (start 1.6891 0.8763) (end 1.6891 -0.8763) (layer F.SilkS) (width 0.06604))
      (fp_line (start 0.9525 -0.8763) (end 1.6891 -0.8763) (layer F.SilkS) (width 0.06604))
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      (fp_line (start 0.29972 0.6985) (end 0.29972 -0.6985) (layer F.SilkS) (width 0.06604))
      (fp_line (start -0.29972 -0.6985) (end 0.29972 -0.6985) (layer F.SilkS) (width 0.06604))
      (fp_line (start -0.29972 0.6985) (end -0.29972 -0.6985) (layer F.SilkS) (width 0.06604))
      (fp_line (start 0.9525 0.8128) (end -0.9652 0.8128) (layer F.SilkS) (width 0.1524))
      (fp_line (start 0.9525 -0.8128) (end -0.9652 -0.8128) (layer F.SilkS) (width 0.1524))
      (fp_line (start -2.47142 -0.98298) (end 2.47142 -0.98298) (layer F.SilkS) (width 0.0508))
      (fp_line (start 2.47142 -0.98298) (end 2.47142 0.98298) (layer F.SilkS) (width 0.0508))
      (fp_line (start 2.47142 0.98298) (end -2.47142 0.98298) (layer F.SilkS) (width 0.0508))
      (fp_line (start -2.47142 0.98298) (end -2.47142 -0.98298) (layer F.SilkS) (width 0.0508))
      (pad 1 smd rect (at -1.41986 0) (size 1.59766 1.80086) (layers F.Cu F.Paste F.Mask)
      (net 1 SDA))
      (pad 2 smd rect (at 1.41986 0) (size 1.59766 1.80086) (layers F.Cu F.Paste F.Mask)
      (net 2 "Net-(0ohm1-Pad2)"))
      )
      (module fab:fab-2X03SMD (layer F.Cu) (tedit 200000) (tstamp 60867A75)
      (at 140.365 113.41)
      (path /60778766)
      (attr smd)
      (fp_text reference J1 (at -0.635 -4.445) (layer F.SilkS)
      (effects (font (size 1.27 1.27) (thickness 0.1016)))
      )
      (fp_text value AVR-UPDI-6 (at 0 4.445) (layer F.SilkS)
      (effects (font (size 1.27 1.27) (thickness 0.1016)))
      )
      (pad 1 smd rect (at -2.54 -2.54) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask)
      (net 3 UPDI))
      (pad 2 smd rect (at 2.91846 -2.54) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask)
      (net 4 VCC))
      (pad 3 smd rect (at -2.54 0) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask)
      (net 5 "Net-(J1-Pad3)"))
      (pad 4 smd rect (at 2.91846 0) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask)
      (net 6 "Net-(J1-Pad4)"))
      (pad 5 smd rect (at -2.54 2.54) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask)
      (net 7 "Net-(J1-Pad5)"))
      (pad 6 smd rect (at 2.91846 2.54) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask)
      (net 8 GND))
      )
      (module fab:fab-1X06SMD (layer F.Cu) (tedit 200000) (tstamp 60868333)
      (at 133.6 117.26)
      (path /60776A4B)
      (attr smd)
      (fp_text reference M1 (at -2.54 0 90) (layer F.SilkS)
      (effects (font (size 1.27 1.27) (thickness 0.1016)))
      )
      (fp_text value FTDI-SMD-HEADER (at 0 0) (layer F.SilkS)
      (effects (font (size 1.27 1.27) (thickness 0.15)))
      )
      (pad 1 smd rect (at 0 -6.35) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask)
      (net 8 GND))
      (pad 2 smd rect (at 0 -3.81) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask)
      (net 9 "Net-(M1-Pad2)"))
      (pad 3 smd rect (at 0 -1.27) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask)
      (net 4 VCC))
      (pad 4 smd rect (at 0 1.27) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask)
      (net 10 TX))
      (pad 5 smd rect (at 0 3.81) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask)
      (net 11 RX))
      (pad 6 smd rect (at 0 6.35) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask)
      (net 12 "Net-(M1-Pad6)"))
      )
      (module VEML6040:VISHAY_VEML6040_1.25X2X1 (layer F.Cu) (tedit 6076B029) (tstamp 60867A90)
      (at 148.175 119.975 180)
      (path /6076B5FF)
      (fp_text reference RGB-colour-sensor1 (at 0.173093 -1.872017) (layer F.SilkS)
      (effects (font (size 0.600325 0.600325) (thickness 0.015)))
      )
      (fp_text value VEML6040 (at 7.414534 1.872654) (layer F.Fab)
      (effects (font (size 0.600529 0.600529) (thickness 0.015)))
      )
      (fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.127))
      (fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.127))
      (fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.127))
      (fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.127))
      (fp_circle (center -2.2 -0.45) (end -2.15 -0.45) (layer F.SilkS) (width 0.127))
      (fp_line (start -1.8 -0.9) (end 1.8 -0.9) (layer F.CrtYd) (width 0.127))
      (fp_line (start 1.8 -0.9) (end 1.8 0.8) (layer F.CrtYd) (width 0.127))
      (fp_line (start 1.8 0.8) (end -1.8 0.8) (layer F.CrtYd) (width 0.127))
      (fp_line (start -1.8 0.8) (end -1.8 -0.9) (layer F.CrtYd) (width 0.127))
      (pad 2 smd rect (at -0.95 0.35 180) (size 0.9 0.35) (layers F.Cu F.Paste F.Mask)
      (net 2 "Net-(0ohm1-Pad2)"))
      (pad 3 smd rect (at 0.9 0.35 180) (size 1 0.35) (layers F.Cu F.Paste F.Mask)
      (net 13 CLK))
      (pad 1 smd rect (at -0.95 -0.35 180) (size 0.9 0.35) (layers F.Cu F.Paste F.Mask)
      (net 8 GND))
      (pad 4 smd rect (at 0.95 -0.35 180) (size 0.9 0.35) (layers F.Cu F.Paste F.Mask)
      (net 4 VCC))
      )
      (module Package_SO:SOIC-8_3.9x4.9mm_P1.27mm (layer F.Cu) (tedit 5D9F72B1) (tstamp 60867AAA)
      (at 140.25 122.025)
      (descr "SOIC, 8 Pin (JEDEC MS-012AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_8.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
      (tags "SOIC SO")
      (path /60769642)
      (attr smd)
      (fp_text reference U1 (at 0 -3.4) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
      )
      (fp_text value ATtiny412-SS (at 0 3.4) (layer F.Fab)
      (effects (font (size 1 1) (thickness 0.15)))
      )
      (fp_line (start 0 2.56) (end 1.95 2.56) (layer F.SilkS) (width 0.12))
      (fp_line (start 0 2.56) (end -1.95 2.56) (layer F.SilkS) (width 0.12))
      (fp_line (start 0 -2.56) (end 1.95 -2.56) (layer F.SilkS) (width 0.12))
      (fp_line (start 0 -2.56) (end -3.45 -2.56) (layer F.SilkS) (width 0.12))
      (fp_line (start -0.975 -2.45) (end 1.95 -2.45) (layer F.Fab) (width 0.1))
      (fp_line (start 1.95 -2.45) (end 1.95 2.45) (layer F.Fab) (width 0.1))
      (fp_line (start 1.95 2.45) (end -1.95 2.45) (layer F.Fab) (width 0.1))
      (fp_line (start -1.95 2.45) (end -1.95 -1.475) (layer F.Fab) (width 0.1))
      (fp_line (start -1.95 -1.475) (end -0.975 -2.45) (layer F.Fab) (width 0.1))
      (fp_line (start -3.7 -2.7) (end -3.7 2.7) (layer F.CrtYd) (width 0.05))
      (fp_line (start -3.7 2.7) (end 3.7 2.7) (layer F.CrtYd) (width 0.05))
      (fp_line (start 3.7 2.7) (end 3.7 -2.7) (layer F.CrtYd) (width 0.05))
      (fp_line (start 3.7 -2.7) (end -3.7 -2.7) (layer F.CrtYd) (width 0.05))
      (fp_text user %R (at 0 0) (layer F.Fab)
      (effects (font (size 0.98 0.98) (thickness 0.15)))
      )
      (pad 1 smd roundrect (at -2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 4 VCC))
      (pad 2 smd roundrect (at -2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 11 RX))
      (pad 3 smd roundrect (at -2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 10 TX))
      (pad 4 smd roundrect (at -2.475 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 1 SDA))
      (pad 5 smd roundrect (at 2.475 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 14 /SCL))
      (pad 6 smd roundrect (at 2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 3 UPDI))
      (pad 7 smd roundrect (at 2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 15 "Net-(U1-Pad7)"))
      (pad 8 smd roundrect (at 2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 8 GND))
      (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-8_3.9x4.9mm_P1.27mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
      )
      )
      (gr_text "ATtiny412+\nVEML6040" (at 148.2 113.425 270) (layer F.Cu)
      (effects (font (size 1 1) (thickness 0.15)))
      )
      (gr_line (start 129.975 107.45) (end 129.975 125.45) (layer Edge.Cuts) (width 0.05) (tstamp 60868437))
      (gr_line (start 136.525 125.45) (end 129.975 125.45) (layer Edge.Cuts) (width 0.05))
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      (segment (start 138.075 124.23) (end 137.775 123.93) (width 0.4) (layer F.Cu) (net 1))
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      EESchema Schematic File Version 4
      EELAYER 30 0
      EELAYER END
      $Descr A4 11693 8268
      encoding utf-8
      Sheet 1 1
      Title ""
      Date ""
      Rev ""
      Comp ""
      Comment1 ""
      Comment2 ""
      Comment3 ""
      Comment4 ""
      $EndDescr
      $Comp
      L MCU_Microchip_ATtiny:ATtiny412-SS U1
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      P 3700 3850
      F 0 "U1" H 3171 3896 50 0000 R CNN
      F 1 "ATtiny412-SS" H 3171 3805 50 0000 R CNN
      F 2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" H 3700 3850 50 0001 C CIN
      F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/40001911A.pdf" H 3700 3850 50 0001 C CNN
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      $EndComp
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      Wire Wire Line
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      $Comp
      L VEML6040:VEML6040 RGB-colour-sensor1
      U 1 1 6076B5FF
      P 7500 3850
      F 0 "RGB-colour-sensor1" H 7500 4520 50 0000 C CNN
      F 1 "VEML6040" H 7500 4429 50 0000 C CNN
      F 2 "VEML6040:VISHAY_VEML6040_1.25X2X1" H 7500 3850 50 0001 L BNN
      F 3 "" H 7500 3850 50 0001 L BNN
      F 4 "MOQ: 2500 pcs" H 7500 3850 50 0001 L BNN "VOLUME"
      F 5 "YES" H 7500 3850 50 0001 L BNN "TAPE_REEL"
      1 7500 3850
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      $EndComp
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      $Comp
      L fab:RES-US1206 0ohm1
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      F 0 "0ohm1" H 6400 4244 45 0000 C CNN
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      1 6400 4050
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      $EndComp
      Wire Wire Line
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      $Comp
      L fab:FTDI-SMD-HEADER M1
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      F 0 "M1" H 5100 2650 45 0001 C CNN
      F 1 "FTDI-SMD-HEADER" H 5100 2650 45 0001 C CNN
      F 2 "fab:fab-1X06SMD" H 5130 2800 20 0001 C CNN
      F 3 "" H 5100 2650 50 0001 C CNN
      1 5100 2650
      1 0 0 -1
      $EndComp
      Text GLabel 4950 2150 0 50 Input ~ 0
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      Text GLabel 4950 2450 0 50 Input ~ 0
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      Wire Wire Line
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      $Comp
      L Connector:AVR-UPDI-6 J1
      U 1 1 60778766
      P 2200 2600
      F 0 "J1" H 1871 2646 50 0000 R CNN
      F 1 "AVR-UPDI-6" H 1871 2555 50 0000 R CNN
      F 2 "fab:fab-2X03SMD" V 1950 2550 50 0001 C CNN
      F 3 "https://www.microchip.com/webdoc/GUID-9D10622A-5C16-4405-B092-1BDD437B4976/index.html?GUID-9B349315-2842-4189-B88C-49F4E1055D7F" H 925 2050 50 0001 C CNN
      1 2200 2600
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      $EndComp
      Text GLabel 4450 3950 2 50 Input ~ 0
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      Wire Wire Line
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      Text GLabel 4450 3550 2 50 Input ~ 0
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      Text GLabel 2750 2500 2 50 Input ~ 0
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      Wire Wire Line
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      Wire Wire Line
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      $Comp
      L Connector:Conn_01x03_Male J2
      U 1 1 607FDCDC
      P 4650 3750
      F 0 "J2" H 4622 3774 50 0000 R CNN
      F 1 "Conn_01x03_Male" H 4622 3683 50 0000 R CNN
      F 2 "Connector_PinHeader_1.27mm:PinHeader_1x03_P1.27mm_Horizontal" H 4650 3750 50 0001 C CNN
      F 3 "~" H 4650 3750 50 0001 C CNN
      1 4650 3750
      -1 0 0 -1
      $EndComp
      Text Label 4300 3650 0 50 ~ 0
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      $EndSCHEMATC
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